![]() ![]() The QPI bandwidth is 96 GB/s for cache coherency and 24 GB/s for I/O. CPUID: 0020020404.Īll models support: XD bit (an NX bit implementation), Hyper-threading, Turbo Boost, VT-i2 (Itanium Virtualization technology), Intel VT-d, RAS with Advanced Machine Check Architecture, Cache Safe technology, Enhanced Demand Based Switching, ECC, two memory controllers each with two SMI links to memory buffers for DDR3, for a combined memory bandwidth of 34 GB/s and capacity of 256 GB. These later generations of Itanium use socket LGA 1248, the QuickPath Interconnect and Scalable Memory Interconnect having replaced the Front-Side Bus used by Itanium 2. ![]() Even though Intel does not use the "Itanium 2" branding for the 9100-series, it's still grouped with Itanium 2 processors because it uses the same platform and is a minor update on the 9000-series. The processors with the Core level Lock-Step error correction feature were released only in 2008. The models with 533 MT/s FSB also support 400 MT/s FSB operation. The chip is similar to Montecito, but the stepping is A1 and the CPUID is 0020010104h. From Montecito onwards all Itaniums are MP-capable. CPUID: 0020000504h (stepping C1) or 0020000704h (stepping C2).Īll processors can support the legacy 400 MT/s FSB. The S-Spec SL75Z was assigned to the chips that Intel sent to HP for use in mx2. This multi-chip module codenamed Hondo is not an Intel product, but a separate project of Hewlett-Packard to pack two CPUs onto one PAC611 socket. The same chip as Madison 9M, but restricted to 2-socket and uniprocessor systems. CPUID: 001F020104h (stepping A1) or 001F020204h (stepping A2).ĩM is the chip of all the third generation Itanium 2s, irrespective of the amount of enabled cache. The same chip as Madison, but at a lower voltage. The Madison 9M table contains the 4MB and 6MB successors of the first Madisons. All Itaniums except some 130 nm models are capable of >2-socket SMP. The 90 nm CPUs (90 series) bring dual-core chips and an updated microarchitecture adding multithreading and splitting the L2 cache into a 256 KB data cache and 1 MB instruction cache per core (the pre-9000 series L2 cache being a 256 KB common cache). Itanium 2 uses socket PAC611 with a 128 bit wide FSB. The FSB data bus is 64 bits wide, not 128 like in Itanium 2. Transistor count: 25.4 million for CPU, 295 million for the external 元 cache. The Itanium from Intel is a high-end server and supercomputer microprocessor.
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